This invention relates to integrated semiconductor devices and methods of manufacture, and more particularly to an improved method of making complementary insulated gate field effect (CMOS) transistors in integrated circuit form.
Complementary FET or "CMOS" devices have long been recognized as offering significant advantages in the area of low power consumption. However, most MOS memory and processor type devices now being manufactured are N-channel because of speed, circuit density and cost factors which heretofore have favored NMOS over CMOS.
It is the principal object of this invention to provide improved CMOS integrated circuit devices and an improved method of making such devices. Another object is to provide CMOS devices and methods of making devices which allow the speed advantage of N-channel transistors to be utilized. A further object is to provide CMOS devices of smaller size or higher circuit density, higher speed and/or lower cost.